Dual-ported shared memory is, for efficiency reasons, an essential component in many multi-bus computer system architectures. For example, FIG. 1 is an architecture block diagram of a high-performance Fibre Channel/SCSI-bus multiplexer that exchanges data transfer commands and data between Fibre Channel networks and SCSI buses. The high-performance Fibre Channel/SCSI-bus multiplexer includes Fibre Channel host adapters 102 and 104, SCSI-bus adapters 106-109, and an internal processor 110 that all access a dual-ported shared memory 112 via an upper Peripheral Component Interconnect ("PCI") bus 114 and lower PCI bus 116. Data is exchanged between Fibre Channel host adapters 102 and 104 and the SCSI-bus adapters 106-109 through buffers allocated from within the dual-ported shared memory 112. Because a high-performance Fibre Channel/SCSI-bus adapter must concurrently, in both directions, transfer data at very high data transfer rates, it is vital that the dual-ported shared memory provide essentially independent channels for both reading and writing the contents of the dual-ported shared memory, and the reading and writing transfers need to transfer data at the data transfer rate provided by the upper PCI bus 114 and lower PCI bus 116 connected to the two ports.
For example, FIG. 2 illustrates a snapshot in time of simultaneous memory accesses of the dual-ported shared memory within the high-performance Fibre Channel/SCSI-bus multiplexer. In FIG. 2, the contents of a memory buffer 202 within the dual-ported shared memory 204 is being read from the first port 206 at the same time that a different memory buffer 208 is being written from the second port 210. This circumstance often arises during a double-buffered transfer of data from a mass storage device controlled by a SCSI adapter to a remote computer system reading data from the mass storage device via a Fibre Channel connection.
Currently-available dual-ported shared memory designs do not support maximally efficient data transfers to two independent ports. FIG. 3 illustrates common deficiencies in currently-available dual-ported shared memory designs. In FIG. 3, a clock signal 302 for a clock driving two computer buses is shown superimposed with the data being transferred on the first computer bus 304 and the data being transferred on the second computer bus 306. For maximal efficiency of data transfer, the dual-ported shared memory should be able to provide the contents of successive memory locations, in the case of a read operation, or receive values to be placed in successive memory locations, in the case of write operations, during each clock cycle. However, in currently-available dual-ported shared memories, the dual-ported shared memory frequently introduces wait states, which are essentially empty or lost clock cycles during which data is not transferred. For example, in the data contents for the first computer bus 304, the dual-ported shared memory was not able to provide or accept data values during clock cycles 308 and 310. Another commonly-occurring problem in currently-available dual-ported shared memories is overhead associated with restarting a data transfer from or to the dual-ported shared memory after the computer bus introduces wait states during the data transfer. For example, in the data transfer for the second computer bus 306, the computer bus stops sending data, for two clock cycles, at clock cycles 312 and 314. At clock cycle 316, the computer bus asserts a signal line on the computer bus to indicate the ability to again receive data from the dual-ported shared memory. However, the dual-ported shared memory then incurs a latency period during clock cycles 316 and 318 and, when the dual-ported shared memory finally begins to resume data transfer, at clock cycle 320, the dual-ported shared memory begins retransmitting data that was previously transferred in the clock cycles 322-325 that immediately preceded the wait cycles 312 and 314 introduced by the second computer bus.
Thus, a need has been recognized in the computer industry for a dual-ported shared memory that can provide a continuous flow of data to two different computer buses. It is desirable that such a dual-ported shared memory be able to support both read and write operations simultaneously to both computer buses without introducing wait states and without retransmitting data following a wait state introduced by either of the computer buses.